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CY7C1049CV33 Automotive
4-Mbit (512 K x 8) Static RAM
4-Mbit (512 K x 8) Static RAM
Features
Functional Description
The CY7C1049CV33 Automotive is a high performance CMOS Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049CV33 Automotive is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Temperature ranges Automotive -A: -40 C to 85 C Automotive-E: -40 C to 125 C High speed tAA = 10 ns Low active power 360 mW (max) 2.0 V data retention Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE
INPUT BUFFER ROW DECODER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
A13 A14
A15
A16
A17
Cypress Semiconductor Corporation Document #: 001-67511 Rev. **
*
198 Champion Court
A18
*
San Jose, CA 95134-1709 *408-943-2600 Revised February 16, 2011
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Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 8 Ordering Information ....................................................... 9 Ordering Code Definitions ........................................... 9 Package Diagrams ......................................................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document #: 001-67511 Rev. **
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Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Automotive-A Automotive-E Automotive-A Automotive-E -10 10 100 - 10 - -12 12 95 - 10 - -15 15 - 95 - 15 Unit ns mA mA mA mA
Pin Configuration
Figure 1. 36-pin SOJ (Top View)
A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC
Figure 2. 44-pin TSOP II (Top View)
NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC
Pin Definitions
Pin Name A0-A18 I/O0-I/O7 NC[1] 36 SOJ Pin Number 44 TSOP II Pin Number I/O Type Input Description Address inputs used to select one of the address locations. 1-5, 14-18, 3-7, 16-20, 20-24, 32-35 26-30, 38-41 7, 8, 11, 12, 9, 10, 13, 14, 25, 26, 29, 30 31, 32, 35, 36 19, 36 1, 2, 21, 22, 23, 24, 25, 42, 43, 44 15 8 37
Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation No Connect No connects. This pin is not connected to the die
WE CE OE
13 6 31
Input/Control Write Enable input, active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/Control Chip Enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power supply inputs to the device.
VSS, GND VCC
10, 28 9, 27
12, 34 11, 33
Note 1. NC pins are not connected on the die.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... -65 C to +150C Ambient Temperature with Power Applied .......................................... -55 C to +125 C Supply Voltage on VCC to Relative GND[2]-0.5 V to +4.6 VDC Voltage Applied to Outputs in High Z State[2] .................................. -0.5 V to VCC + 0.5 V Input Voltage[2] .................................... -0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Automotive-A Automotive-E Ambient Temperature -40 C to +85 C -40 C to +125 C VCC 3.3 V 0.3 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX ICC ISB1 ISB2 Description Test Conditions -10 Min 2.4 - 2.0 -0.3 GND < VI < VCC VCC = Max, f = fMAX = 1/tRC Auto-A Auto-E VCC Operating Supply Current Auto-A Auto-E Auto-A Auto-E Auto-A Auto-E -1 - - - - - - - Max - 0.4 VCC + 0.3 0.8 +1 - 100 - 40 - 10 - 2.4 - 2.0 -0.3 -1 - - - - - - - -12 Min Max - 0.4 VCC + 0.3 0.8 +1 - 95 - 40 - 10 - 2.4 - 2.0 -0.3 - -20 - - - - - - -15 Min Max - 0.4 VCC + 0.3 0.8 - +20 - 95 - 45 - 15 mA mA mA mA mA Unit V V V V A
Output HIGH Voltage VCC = Min; IOH = -4.0 mA Output LOW Voltage VCC = Min; IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[2] Input Load Current
Automatic CE Max. VCC, CE > VIH; Power Down Current VIN > VIH or VIN < VIL, f = fMAX --TTL Inputs Max. VCC, CE > VCC - 0.3 V, Automatic CE Power Down Current VIN > VCC - 0.3 V, or VIN < 0.3 V, --CMOS Inputs f=0
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter[3] CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter[3] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 36-pin SOJ 46.51 18.8 44-pin TSOP-II 41.66 10.56 Unit C/W C/W
JA JC
Notes 2. VIL (min) = -2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
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Figure 3. AC Test Loads and Waveforms [4]
10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V 12-, 15-ns devices: 3.3 V OUTPUT 30 pF R2 351 R 317
Z = 50
30 pF*
(a)
High Z characteristics: 3.3 V 90% 10% OUTPUT 5 pF
(b)
R 317
3.0 V GND
Rise Time: 1 V/ns
ALL INPUT PULSES 90% 10%
R2 351
(c)
Fall Time: 1 V/ns
(d)
Notes 4. AC characteristics (except High Z) for 10 ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
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AC Switching Characteristics
Over the Operating Range [5] -10 Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High Z[7, 8] Z[7, 8] CE LOW to Low Z[8] CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7, 8] 100 10 - 3 - - 0 - 3 - 0 - 10 7 7 0 0 7 5 0 3 - - - 10 - 10 5 - 5 - 5 - 10 - - - - - - - - - 5 100 12 - 3 - - 0 - 3 - 0 - 12 8 8 0 0 8 6 0 3 - - - 12 - 12 6 - 6 - 6 - 12 - - - - - - - - - 6 100 15 - - - - 0 - 3 - 0 - 15 10 10 0 0 10 7 0 3 - - - 15 3 15 7 - 7 - 7 - 15 - - - - - - - - - 7 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max Min -12 Max Min -15 Max Unit
Write Cycle [9, 10]
Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) ofFigure 3 on page 5. Transition is measured 500 mV from steady-state voltage. 8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 16 tHZOE
Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycles. 13. Address valid before or similar to CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 16. During this period, the I/Os are in output state. Do not apply input signals.
tHD
DATA VALID
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Switching Waveforms
(continued) Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [17]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H L L L OE X L X H WE X H L H High Z Data Out Data In High Z I/O0-I/O7 Power Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the I/Os are in output state. Do not apply input signals.
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Ordering Information
Speed (ns) 10 12 15 Ordering Code CY7C1049CV33-10VXA CY7C1049CV33-12ZSXA CY7C1049CV33-15VXE CY7C1049CV33-15ZSXE Package Diagram 51-85090 51-85087 51-85090 51-85087 Package Type 36-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP II (Pb-free) 36-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP II (Pb-free) Operating Range Automotive-A Automotive-A Automotive-E Automotive-E
Ordering Code Definitions
CY 7C 1 04 9 C V33 - XX XX X X Temperature Range: X = A or E A = Automotive-A or E = Automotive-E X = Pb-free; X Absent = Leaded Package Type: XX = V or ZS V = 36-pin Molded SOJ ZS = 44-pin TSOP II Speed Grade: XX = 10 ns or 12 ns or 15 ns V33 = 3.0 V to 3.6 V Process Technology: C 150 nm Data width: x 8-bits 4-Mbit density Fast Asynchronous SRAM Marketing Code: 7C = SRAMs Company ID: CY = Cypress
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Package Diagrams
Figure 8. 36-pin (400-Mil) Molded SOJ, 51-85090
51-85090 *E
Figure 9. 44-pin TSOP II, 51-85087
51-85087 *C
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Acronyms
Acronym CMOS CE OE RAM I/O SOJ TTL TSOP WE Chip Enable Output Enable Random Access Memory Input/Output small outline J-lead transistor-transistor logic thin small outline package Write Enable Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol ns V s A mA mm ms MHz pF % mW W C ohms nano seconds Volts micro seconds micro Amperes milli Amperes milli meter milli seconds Mega Hertz pico Farad percent milli Watts Watts degree Celcius Unit of Measure
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Document History Page
Document Title: CY7C1049CV33 Automotive 4-Mbit (512 K x 8) Static RAM Document Number: 001-67511 Rev. ** ECN 3186792 Orig. of Change PRAS Submission Date Description of Change
03/03/2011 Separation of the automotive datasheet from CY7C1049CV33 spec no. 38-05006 Rev. *J. Further rev of 38-05006 would include only industrial / commercial parts.
Document #: 001-67511 Rev. **
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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(c) Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-67511 Rev. **
Revised February 16, 2011
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